A Dual-issue, RISC-based DSP Core with emphasis on Code Density
碩士 === 國立清華大學 === 資訊工程學系 === 88 === We design a RISC-based DSP core. We focus on performance and code density. We use VLIW and SIMD techniques in our design to provide higher computation power. Moreover, we combine some instructions into a compound instruction to improve code density. We have implem...
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2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/86260831630824347086 |
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ndltd-TW-088NTHU03920322016-07-08T04:23:16Z http://ndltd.ncl.edu.tw/handle/86260831630824347086 A Dual-issue, RISC-based DSP Core with emphasis on Code Density 一個高程式碼密度且具雙指令執行特性及精簡指令集架構的數位訊號處理器核心 Jeng-Yun Hsu 徐正運 碩士 國立清華大學 資訊工程學系 88 We design a RISC-based DSP core. We focus on performance and code density. We use VLIW and SIMD techniques in our design to provide higher computation power. Moreover, we combine some instructions into a compound instruction to improve code density. We have implemented the DSP core in synthesizable RTL Verilog. The core is able to run at 120 MHz when targeted towards a TSMC 0.35 um cell library. Youn-Long Lin 林永隆 2000 學位論文 ; thesis 41 en_US |
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NDLTD |
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en_US |
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Others
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NDLTD |
| description |
碩士 === 國立清華大學 === 資訊工程學系 === 88 === We design a RISC-based DSP core. We focus on performance and code density. We use VLIW and SIMD techniques in our design to provide higher computation power. Moreover, we combine some instructions into a compound instruction to improve code density. We have implemented the DSP core in synthesizable RTL Verilog. The core is able to run at 120 MHz when targeted towards a TSMC 0.35 um cell library.
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| author2 |
Youn-Long Lin |
| author_facet |
Youn-Long Lin Jeng-Yun Hsu 徐正運 |
| author |
Jeng-Yun Hsu 徐正運 |
| spellingShingle |
Jeng-Yun Hsu 徐正運 A Dual-issue, RISC-based DSP Core with emphasis on Code Density |
| author_sort |
Jeng-Yun Hsu |
| title |
A Dual-issue, RISC-based DSP Core with emphasis on Code Density |
| title_short |
A Dual-issue, RISC-based DSP Core with emphasis on Code Density |
| title_full |
A Dual-issue, RISC-based DSP Core with emphasis on Code Density |
| title_fullStr |
A Dual-issue, RISC-based DSP Core with emphasis on Code Density |
| title_full_unstemmed |
A Dual-issue, RISC-based DSP Core with emphasis on Code Density |
| title_sort |
dual-issue, risc-based dsp core with emphasis on code density |
| publishDate |
2000 |
| url |
http://ndltd.ncl.edu.tw/handle/86260831630824347086 |
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