A Dual-issue, RISC-based DSP Core with emphasis on Code Density
碩士 === 國立清華大學 === 資訊工程學系 === 88 === We design a RISC-based DSP core. We focus on performance and code density. We use VLIW and SIMD techniques in our design to provide higher computation power. Moreover, we combine some instructions into a compound instruction to improve code density. We have implem...
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| Format: | Others |
| Language: | en_US |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/86260831630824347086 |
| Summary: | 碩士 === 國立清華大學 === 資訊工程學系 === 88 === We design a RISC-based DSP core. We focus on performance and code density. We use VLIW and SIMD techniques in our design to provide higher computation power. Moreover, we combine some instructions into a compound instruction to improve code density. We have implemented the DSP core in synthesizable RTL Verilog. The core is able to run at 120 MHz when targeted towards a TSMC 0.35 um cell library.
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