| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 88 === In this thesis, we present two Blowfish encryption chips (BECs) based on the Blowfish algorithm. BECs are microprocessor peripheral devices and might be useful for network devices. They use a 64-bit user-specified key to encrypt and decrypt 64-bit blocks of data. BECs can be used in real time applications and variety of Electronic Funds Transfer applications.
To realize the BECs, we use VHDL''87, Synplify, and Maxplus; for designing, synthesizing and simulating. Field Programmable Gate Arrays (FPGAs) are chosen as our target hardware environment.
The first design of BEC for area requires 741 logic cells. The maximum operating clock is 42.55 MHz and the corresponding data throughput is about 21.28 Mbit/s. The second design of BEC for speed requires 4698 logic cells. The maximum operating clock is 54.9 MHz and the corresponding data throughput is about 43.92 Mbit/s.
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