Embedded DSP Core Architecture for Communication Applications

• Main Authors: Jin-Mao Liu, 劉金茂
• Other Authors: Shyh-Jye Jou
• Format: Others
• Language: zh-TW
• Published: 2000
• Online Access: http://ndltd.ncl.edu.tw/handle/15637295376602737195

碩士 === 國立中央大學 === 電機工程研究所 === 88 === Today, DSP processors are at the heart of many communication systems and embedded systems. The object of this thesis is to develop a DSP processor architecture that is suitable to be parameterized by user specification to obtain a DSP processor that has the characteristics of low cost, reusable, and short time-to-market. In this thesis, we survey several DSP processor architectures and the scheme of parameterized DSP processor core in recent years. Then, we propose a DSP processor architecture that can be parameterized. In addition, we also address the addressing modes in the DSP processor according to the characteristic of DSP algorithm. For high performance DSP processor, we also modify the architecture of MAC unit and design suitable pipeline stages in the processor. We also propose the solutions of pipeline hazard to resolve the pipeline stall. Finally, the DSP processor is described with Verilog hardware description language and synthesized by Synopsys. From the synthesis reports, the total gate counts are 27915.418 gates and can operate in 100MHz.