低雜訊輸出緩衝器設計及USB2實體層的時脈回復器製作

• Main Author: 邱瑞德
• Other Authors: 周世傑
• Format: Others
• Language: zh-TW
• Published: 2000
• Online Access: http://ndltd.ncl.edu.tw/handle/56317123013185524584

碩士 === 國立中央大學 === 電機工程研究所 === 88 === Abstract High speed I/O is the key component to successfully transmit data between electronic devices. There are two research topics in this thesis. First we focus on the overview of simultaneous switching noise (SSN). We will propose an output buffer for reducing SSN, output signal ringing and maintain DC current capability. Also we provide a program to estimate power pads for SSO. Second, a clock recovery architecture and circuit is proposed for Universal Serial Bus 2 (USB2) high-speed mode (480M bits per second). USB2 is a new serial bus standard for the peripheral of PC today. The physical layer of USB2 consists of a transceiver and the clock recovery (CR). For USB2 high-speed 480M bits per second, it is important to design an all digital, low power, small area clock recovery. In this thesis, we propose an overall architecture of USB2 physical layer. We also propose a new all digital clock recovery for USB2 physical layer. However, it consume only when working at 480M bit per second.