An Application Specific Processor for MELP Speech CodingProcessing

• Main Authors: Chien-Chih Chen, 陳建志
• Other Authors: Chin-Teng Lin
• Format: Others
• Language: en_US
• Published: 2000
• Online Access: http://ndltd.ncl.edu.tw/handle/62992474021220893495

碩士 === 國立交通大學 === 電機與控制工程系 === 88 === Speech communication is the most dominant and common service in telecommunication at present. Digital transmission of speech is more elasticity, providing the opportunity of achieving cost, consistent quality, security and spectral efficiency in the systems that exploit it. Due to the increase in number of users and limited bandwidth available, the transmission rate of new digital speech coding techniques has dropped from 8Kbps(CELP), 4.8Kbps(CS-ACELP) to 2.4Kbps(MELP). As the bit rate falling, the speech quality can only be maintained by employing very complex algorithms which are difficult to implement in FAST speech coding. This thesis investigates a new application specific processor for speech coding processing. The processor is designed to process Mixed Excitation Linear Prediction (MELP) coding which is the best and common speech compression. We use hardware-software codesign methodology to optimize the processor architecture and instruction set. The processor uses a five-stage pipeline to balance performance and core area. It has two memory banks for vector operation, four-level recurrent loops, multi-layer stacks, 24-bit floating-point unit for precision, 8-bit exponent unit for large dynamic range operation and special instructions for parallel operation. Each instruction length is fixed as 24 bits. The processor provide six special addressing modes and 3-operand operations. The chip is realized by using a TSMC 0.35μm 1P4M CMOS fabrication and synthesis by COMPASS cell library. The silicon area required for the core is approximately11.56 .