Hardware Design and Implementation of Frame-based Fair Queuing Scheduler

• Main Authors: Ko Ching Yu, 柯菁郁
• Other Authors: Tsern-Huei Lee
• Format: Others
• Language: zh-TW
• Published: 2000
• Online Access: http://ndltd.ncl.edu.tw/handle/78280655381123085893

碩士 === 國立交通大學 === 電信工程系 === 88 === With the coming of the Internet new era, the network evolution trends to be wide band and intelligent. Also, because of the mergence of traditional telecom industry and network industry, in today's network, many types of application, such as voice over IP, video conference and so on, request real-time service. Therefore, these applications often request quality of service (QoS) guarantee to certain degree. In the recent years, the traffic on the Internet increases rapidly. As a result, conventional routers become network bottleneck. Using the specific hardware to process packets is the better solution to solve the problem of speed. In this thesis, we choose FFQ (Frame-based fair queueing) scheduling algorithm to implement scheduler hardware for the fixed length case, and propose the scheme for the variable length case to reduce the complexity of implementation. Our scheme is efficient and simple, and thus is very attractive for hardware implementation in high-speed network.