| Summary: | 碩士 === 國立交通大學 === 電子工程系 === 88 === Electrostatic Discharge(ESD) protection has become more and more important as the device feature size scales down. In daily lives, the charging process occurs when two dissimilar materials rub together and then separate. Throughout the integrated circuit’s overall operation time, any contact with another object can result in a discharging process and catastrophic damage, especially for CMOS IC. In such circuits, the input/output pins are usually connected to internal gate oxide that is about 50~70Å thick in present submicron process technologies. A 10 V DC voltage can easily cause gate oxide wear-out. However, a 2 kV transient voltage or greater is generated when ESD occurs. Thus, an efficient ESD protection scheme is inevitably needed.
This thesis extensively explores the ESD protection device in 0.30mm gate length nMOS transistor. The device is widely utilized in the input/output stages for ESD protection and its ESD capability is found to be related to epi-layer thicknesses. In this work, the existing substrate current model and avalanche generation model are cited to investigate parameter dependence on epi-layer thicknesses. Finally, we try to build up a high-current bipolar snapback I-V model to characterize the ESD protection mechanism of nMOS transistor.
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