The Design of A New CMOS Imager Using Log-Domain Passive Pixel Sensors

• Main Authors: Hou-Bo Cheng, 陳厚柏
• Other Authors: Prof. Chung-Yu Wu
• Format: Others
• Language: zh-TW
• Published: 2000
• Online Access: http://ndltd.ncl.edu.tw/handle/51647980565989796187

碩士 === 國立交通大學 === 電子工程系 === 88 === Recently, there has been a growing interest in CMOS image sensors. The major reason for this interest is the customer demand for miniaturized, low-power, and low-cost digital cameras. CMOS image sensors offer a great potential to integrate a significant amount of VLSI electronics on a single chip and reduce discrete components and packaging costs. It is now straightforward to envision a single-chip camera that has integrated timing and control electronics, sensor array, signal processing electronics, analog-to-digital converter (ADC) and full digital interface. Such a camera-on-a-chip will operate with standard logic supply voltages and consume power measured in the tens of milliwatts. The pixel size is the key point for CMOS image sensors in high-resolution applications. In this thesis, the structure of two-transistors in a pixel is proposed. Due to the reduction of the number of transistors in a pixel , the pixel size is as small as 6.15x6.05 m2 and the fill factor is 21%. The P-diffusion/N-well with the P-implant region inside the thin-oxide region is proposed for the photodiode. It is anti-blooming and has low leakage current induced nearly the bird’s beak. The correlated double sampling (CDS) technique and output amplifier are used to reduce the fixed pattern noise (FPN) and amplify the signal voltage, respectively. A 128x128 CMOS image sensor including image array, decoder, readout circuit, fabricated by 0.5m Double-Poly-Double-Metal (DPDM) N-well CMOS technology has been measured. The pixel rate is 10MHz, and power consumption is 64mW at 5V power supply.