Manchester Carry Chain Adder Research
碩士 === 國立交通大學 === 電子工程系 === 88 === This thesis discusses the adder based on Manchester carry chain. The Manchester carry chain circuit based on pass-transistors and dynamic logic techniques have the smallest transistor count among all carry look-ahead circuits including domino and other s...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/65144323390590147038 |
| Summary: | 碩士 === 國立交通大學 === 電子工程系 === 88 === This thesis discusses the adder based on Manchester carry chain. The Manchester carry chain circuit based on pass-transistors and dynamic logic techniques have the smallest transistor count among all carry look-ahead circuits including domino and other static techniques. We introduce new bypass circuit、new output buffer and carry-chain buffer. Then we design a 64-b adder based on the circuits introduced on the thesis.
The analysis data based on TSMC 0.6μm SPDM CMOS technology got by HSPICE.
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