On Address Register Allocation for Code Generation of Embedded Systems
碩士 === 國立交通大學 === 電子工程系 === 88 === The embedded system design prevails in recent years. The code size becomes an important issue because of the limited storage capacity on the chip. Besides, it may affect the performance of the execution for the function. In this thesis, we pro...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2000
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/47066186377134139686 |
| Summary: | 碩士 === 國立交通大學 === 電子工程系 === 88 === The embedded system design prevails in recent years. The code size becomes an important issue because of the limited storage capacity on the chip. Besides, it may affect the performance of the execution for the function.
In this thesis, we propose an algorithm to reduce the code size in the loop segments. The proposed algorithm can find the optimal address register allocation for loop codes subject to the constraints on the number of address registers. The experimental results show significant reductions on the code size for some codes. However, the algorithm doesn’t improve the DSP’s benchmark circuits very much because those codes are already well written. The compiler can therefore use the technique to produce more efficient codes for the embedded systems.
|
|---|