| Summary: | 博士 === 國立交通大學 === 電子工程系 === 88 === In this dissertation, we firstly investigate the narrow-width effects of polysilicon thin film transistors (poly-Si TFTs). With reducing channel width, TFT characteristics such as mobility, threshold voltage, and subthreshold swing are found to improve dramatically. To gain insight on the origin of the narrow-width effects, a physically-based analytical mode is proposed to simulate the output characteristics of poly-Si TFTs. Excellent fitting with the experimental data is observed over a wide range of drain bias, gate bias, and channel width. Our model shows that both the deep state density and tail state density are reduced with reducing channel width, thus accounting for the improved TFT characteristics with reducing channel width. In addition, subthreshold swings of poly-Si TFTs with various channel widths and lengths are compared. It is found the subthreshold swings of poly-Si TFTs with the same channel area are identical, indicating that the grain-boundary trap density is reduced due to the reduction of channel area.
The short-channel effects of poly-Si TFTs are also investigated. For n-channel devices, because of the larger impact-ionization rate of electrons, their characteristics are affected by the avalanche multiplication as well as floating-body effect. As a result, both the threshold voltage and subthreshold swing are reduced and kink effect occurs when the channel length is small and drain bias is large. Since the short-channel effects are related to the grain-boundary trap density, the reduction of trap density due to scaling down the channel width can suppress the avalanche multiplication and enhance the gate bias control over the poly-Si channel. Furthermore, the trap density of passivated devices is reduced significantly, which in turn effectively suppress the avalanche multiplication. Consequently, the increased subthreshold swing due to punch-through effect rather than reduced subthreshold swing caused by avalanche multiplication is observed. As for p-channel devices, because of the small impact-ionization rate of holes, the avalanche-multiplication effect is not pronounced. Therefore, with scaling down the channel length and thus reducing trap density, the characteristics of p-channel devices are improved.
We have also proposed a new lightly-doped-drain structure to reduce the anomalous leakage current of poly-Si TFTs. Since the liquid phase deposition (LPD) oxide can selectively deposit on the surface of poly-Si but not on the surfaces of photoresist and silicon nitride, the oxide spacer of this new device is formed by selective deposition of LPD oxide on the exposed sidewall of polycrystalline silicon gate. The process is simple, inexpensive, and can be performed at room temperature. Besides, the oxide spacer is self-aligned to the poly-Si gate. Our experimental results show that LPD oxide spacer of this new device is effective in reducing the electric field in the depletion region near the drain side. Compared to the device without oxide spacer, the leakage current of the new device is reduced dramatically and ON/OFF current ratio is improved by more than one order of magnitude. In addition, the kink effect is less pronounced and the reliability is improved in the new device.
The characteristics of invert-staggered amorphous silicon (a-Si: H) TFT with a bottom gate is influenced by the interface at amorphous silicon and silicon nitride, and thus is influenced by the morphology of the Al bottom-gate metallurgy. We proposed a new method which combine the chemical mechanical polishing and high deposition temperature of Al gate to improve performance of inverted-staggered a-Si: H TFTs. We found that although the surface roughness of the as-deposited Al films increases with increasing deposition temperature, Al films deposited at higher temperature are more robust to hillock formation during subsequent annealing. To take advantage of the better hillock suppression properties, chemical mechanical polishing technique is employed to reduce the inherently large surface roughness of these high-temperature-deposited Al films. Our results show that the electrical characteristics of the TFTs are significantly improved. Specifically, the threshold voltage is reduced from 2.37 V to 1.43 V, the mobility is improved from 0.32 cm2/V-s to 1.36 cm2/V-s, and the subthreshold swing is improved from 0.72 V/decade to 0.58 V/decade as the Al deposition temperature is increased from 25 OC to 400 OC.
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