| Summary: | 博士 === 國立交通大學 === 電子工程系 === 88 === Abstract
The main goal of this thesis is to improve the refresh time of DRAM cell. It can be accomplished by two approaches. The first approach is to increase the storage capacitance of the cell, while the other approach is to reduce the junction leakage current of DRAM cell. For increased storage capacitance, polycrystalline silicon film with a rugged surface (i.e., rugged poly-Si) was applied. The rugged-poly was deposited by a single-wafer rapid thermal chemical vapor deposition (RTCVD) system, suitable for 12-inch wafer fabrication. In this thesis, the rugged poly-Si films have been successfully fabricated to serve as the bottom storage electrode for the stacked capacitor in dynamic random access memory cells. Our study suggests that the rugged poly-Si is actually formed by the nucleation generation on the amorphous silicon surface and subsequent crystalline growth during the annealing step following deposition. An effective surface area of approximately 2.9 times that of a conventional poly-Si film electrode is obtained.
In addition, we have fabricated and studied the electrical and physical characteristics of Ta2O5 films on rapid thermal nitrided (RTN) rugged polycrystalline silicon electrodes for 256M dynamic random access memory (DRAM) application. To overcome the higher leakage current on Ta2O5 films with rugged poly-Si bottom electrodes, we have successfully employed a light oxidation on rugged poly-Si grains for improving the acute angle of surface morphology, and a post-treatment with rapid thermal nitridation of N2O on Ta2O5 films to reduce the leakage current. The successful integration of Ta2O5 film with rugged poly-Si makes it very promising for future 256M dynamic random access memory (DRAM) application.
Since the retention time distribution of DRAM consists of a ‘tail distribution’ and a ‘main distribution’. Increasing the storage capacitance only improves the ‘main distribution’ of the DRAM array, but it does not change the tail distribution. Since the refresh characteristics of a DRAM array are determined by the worst-case bits represented by the ‘tail distribution’, so increasing the storage capacitance does not improve the overall refresh characteristics of the DRAM array. The ‘tail distribution’ is found to be affected by thermionic field emission (TFE) current of dislocation and stacking faults, while the ‘main distribution’ is affected by generation-recombination (G-R) current of SiO2/Si interface trapped center and H-atom trapped center. We have performed a detailed study, and found that the ‘tail distribution’ is affected by HDP, furnace oxidation, and etching profile processes. In contrast, we found that the ‘main distribution’ is strongly affected by H2 plasma treatment, and HDP trench filling processes. In this thesis, we have also performed a detailed study on how to optimize shallow trench isolation for DRAM application. The retention time distribution is improved in new DRAM generation by the new STI isolation process. However, the degree of improvement is retarded if furnace linear oxide linear is used. The control of defect generation is therefore very important to improve the retention time distribution.
Finally, the effects of contact resistance of the refresh characteristics of DRAM cell were studied. Silicidation process is optimized in order to obtain low contact resistance. We found that the contact resistance of the sample with TiN capping layer is lowered by 10-15% and the nature good yield (minimum refresh time of DRAM up to 80 ms) is higher by 19.7% than those of the sample without TiN capping layer,.
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