Architectures and CAD for Dynamically Reconfigurable Field-Programmable Gate Arrays
博士 === 國立交通大學 === 資訊科學系 === 88 === Improving logic efficiency by time-sharing, Dynamically Reconfigurable FPGAs (DRFPGAs) have attracted much attention recently. In a DRFPGA, a virtual large design is partitioned into multiple stages (or partitions) to share the same smaller physical device than tha...
Main Authors: | Guang-Ming Wu, 吳光閔 |
---|---|
Other Authors: | Yao-Wen Chang |
Format: | Others |
Language: | en_US |
Published: |
2000
|
Online Access: | http://ndltd.ncl.edu.tw/handle/51836091379064272536 |
Similar Items
-
Energy-aware architectures, circuits and CAD for field programmable gate arrays
by: Honoré, Francis
Published: (2007) -
A Field Programmable Gate Array Architecture for Two-Dimensional Partial Reconfiguration
by: Wang, Fei, Dr.
Published: (2006) -
Reconfigurable wavelet-based architecture for pattern recognition applications using a field programmable gate array
by: Al-aqeeli, Abulqadir
Published: (1998) -
Reconfigurable design for pattern recognition using field programmable gate arrays
by: Sareen, Aman
Published: (1999) -
A secure single clock cycle reconfigurable field programmable gate array
by: Millar, James
Published: (2013)