| Summary: | 博士 === 國立交通大學 === 資訊科學系 === 88 === Improving logic efficiency by time-sharing, Dynamically Reconfigurable FPGAs (DRFPGAs) have attracted much attention recently. In a DRFPGA, a virtual large design is partitioned into multiple stages (or partitions) to share the same smaller physical device than that occupied by a traditional FPGA.
DRFPGAs interconnection resources consist of pre-fabricated wire segments and programmable switches. Routing in DRFPGAs is performed by programming the switches to connect the wire segments. The switches usually have high resistance and capacitance, and consume a large amount of area. It is thus of particular importance to design switch modules that maximize routability under the area and delay constraints.
Because the logic and interconnect needed for a circuit is time-multiplexed on a DRFPGA, its partitioning and placement problems are different from their traditional ones. The major difference is that the execution order of circuit elements must follow the precedence and capacity constraints in the DRFPGAs. The partitioning and placement algorithms determine the number of interconnections needed by a DRFPGA and greatly affect routing. Thus it is desirable to develop effective partitioning and placement to minimize the interconnection cost.
This thesis focuses on two important issues for DRFPGAs: architectures and CAD algorithms.
Architectures:
There are two types of switch modules: switch matrices and switch blocks. In this thesis, we present quasi-universal switch matrices which have the maximum possible routing capacities among all switch matrices of the same size. Next, we propose methods for designing and analyzing universal switch blocks which are cheapest for three-dimensional FPGAs.
CAD algorithms:
In this thesis, we present generic integer linear programming (ILP) formulations for the multi-stage precedence-constrained partitioning problems. The ILP-based formulations are so flexible that they can readily apply to the partitioning problems with various objectives and constraints. Next, we introduce a new placement problem motivated by the special DRFPGA architectures. For the placement, we develop an effective metric that can consider wirelength, storage requirement, and power consumption simultaneously. With the considerations of the new metric and the precedence constraints, we then present a three-stage scheme of partitioning, initial placement generation, and placement refinement to solve the new placement problem.
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