Speculative Memory Accesses in Superscalar Multiprocessing

• Main Authors: Neng-Pin Lu, 盧能彬
• Other Authors: Chung-Ping Chung
• Format: Others
• Language: en_US
• Published: 2000
• Online Access: http://ndltd.ncl.edu.tw/handle/60106227946455163432

博士 === 國立交通大學 === 資訊工程系 === 88 === Superscalar multiprocessors can exploit both coarse-grained and fine-grained parallelism in programs. But the continuing widening gap between processor and memory speeds can quickly offset any performance gains expected from the parallelism exploitation of superscalar processing and multiprocessing. To solve the memory latency problem, there have been several mechanisms, such as multithreading, relaxed memory consistency, and data prefetching, proposed. On the other hand, in superscalar processing, speculative execution not only exploits instruction-level parallelism but also hides memory latencies. However, to guarantee correct program execution, the dynamic scheduling capabilities of superscalar processors should be restrict to the access constraints under certain memory consistency models in the superscalar multiprocessor system. As a result, parallelism exploitation and latency hiding may be severe constrained. To break the constraints, speculative memory accesses are vital in superscalar multiprocessing. In this dissertation, we investigate speculative memory access techniques in superscalar multiprocessing. First, in order to enable accurate simulation of multiprocessing systems, we developed a simulator, called SMINT, for superscalar multiprocessing systems. With this simulator, we examined the exploitable parallelism in superscalar processing and multiprocessing. We found that the parallelism in programs can best be exploited with a moderate degree of superscalar processing and a high degree of multiprocessing. Based on the measurement of parallelism, we considered the load/store unit design for superscalar processors to support speculative memory access techniques. Finally, we investigated the memory design issues for speculative memory accesses in superscalar multiprocessing. Previous research shown speculation of load instructions may hide memory access latencies, but early speculation is likely to fail. To increase the success rate of speculative loads, speculation of store instructions is beneficial. While store instructions are destructive to the memory system. To support speculative store, we use speculative write cache and design a new cache coherence protocol to support cache-to-cache lookahead data transfer and reduce interprocessor communication latencies. Through the investigation of this dissertation, we built a superscalar multiprocessor simulator, investigated the parallelism exploitation in superscalar mulitprocessing, and developed the speculative store technique. We hope this research can contribute to the exploitation of parallelism in multiprocessing systems.