Using Hotelling T2 Control Chart for Clustered Defects in IC Fabrication

碩士 === 國立交通大學 === 工業工程與管理系 === 88 === All industrial manufacturers ultimately strive to obtain maximum profits. For the integrated circuits (IC) manufacturer, the yield on each wafer is an important index to evaluate profit. During the complicated manufacturing process of a wafer, defects on the waf...

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Bibliographic Details
Main Authors: Wu Chao-Hwa, 吳炤華
Other Authors: Prof. Lee-Ing Tong
Format: Others
Language:zh-TW
Published: 1999
Online Access:http://ndltd.ncl.edu.tw/handle/29728798775221598355
Description
Summary:碩士 === 國立交通大學 === 工業工程與管理系 === 88 === All industrial manufacturers ultimately strive to obtain maximum profits. For the integrated circuits (IC) manufacturer, the yield on each wafer is an important index to evaluate profit. During the complicated manufacturing process of a wafer, defects on the wafer surface are nearly impossible to avoid. Some defects permanently damage the chips, subsequently leading to yield loss. In addition, the extent of defect-clustering is also another important factor to affect yield loss. To enhance the yield of IC products, most manufacturers use control charts for their statistical process control (SPC) under controlling defects. Generally, the attribute control chart has been utilized to monitor the defect counts on a wafer. However, this control chart for defects may cause erroneous results without the consideration of the clustered defects. In this study, we present a novel means of constructing a Hotelling T2 control chart that can detect defects and defect-clustering simultaneously. A case study is also presented, demonstrating the effectiveness of the proposed control chart.