Methodology of Hierarchical Interface Design and Modeling - A case study for MPEG-2 video decoding
碩士 === 國立成功大學 === 電機工程學系 === 88 === More and more circuit can be put into one chip because of the continuing improvement on the production technique of semi-conductor. In order to short the developing time frame for System on a chip (SOC), how to systemize the description、 regulate the in...
Main Authors: | , |
---|---|
Other Authors: | |
Format: | Others |
Language: | zh-TW |
Published: |
2000
|
Online Access: | http://ndltd.ncl.edu.tw/handle/12587986923214656824 |
id |
ndltd-TW-088NCKU0442173 |
---|---|
record_format |
oai_dc |
spelling |
ndltd-TW-088NCKU04421732015-10-13T10:57:08Z http://ndltd.ncl.edu.tw/handle/12587986923214656824 Methodology of Hierarchical Interface Design and Modeling - A case study for MPEG-2 video decoding 階層式介面電路模型與設計法則之研究-以MPEG-2視訊解碼器為例 Hsiao-cheng Wang 王效誠 碩士 國立成功大學 電機工程學系 88 More and more circuit can be put into one chip because of the continuing improvement on the production technique of semi-conductor. In order to short the developing time frame for System on a chip (SOC), how to systemize the description、 regulate the interface circuit among each intellectual property to get best design & connect each IP to complete the design of entire system chip has become a very important & disturbing subject for designers. Each connecting component has its own feature, and sometimes this could be very complicated. Main topic of this report is to find out how to clearly express & regulate system chip on the interface circuit in order to design an effective circuit to integrate every connecting component. We have provided the following solutions for description & regulation of interface circuit and problem for effective design. First, we’ve analyzed the data transaction behavior among each component in every level and submit a description framework for a systemized level data transaction behavior. This structure can catch the data transaction behavior inside a system completely in a systemized description way under different levels. It can also allow the designers to have fully control of regulations for data transmitting behavior to increase the rate for successful chip integration design. The whole structure can be divided into four levels in order to describe this kind of behavior: algorithm level, functional level, virtual component level & state transition level. Secondly, we use this structure to complete level design of interface circuit quickly by analyzing behavior features of data transaction among components in every system, building a corresponding triple interface design model, modifying each level’s necessary design features. The hierarchical interface design models we proposed are: abstract interface design model, virtual component interface design model, and state-level interface circuit design model. In this model, abstract interface design model is used to catch system’s data transaction characteristic in application and function level. Virtual component interface design model is used to describe both software and hardware’s abstract data transmission features in the system that is not related with the type of interface circuit to use. State-level interface circuit design model is used to identify the necessity of interface circuit and to design the whole circuit. Finally, we develop a new and perfect interface design and practical method based on above mentioned multi-level data transmission structure and design model to analyze different circuit application principals. It allows us not only to describe and fulfill interface circuit of abstract data transmission behavior but also to systemize all the solutions for incompatible problems between connecting components and standardize design templates. The two advantages can work out the design problems on different levels. Take MPEG II video decoding system as an example, we’ve applied the multi-level circuit design method, model and description structure that we developed to complete the four interface circuit design among each component. The result shows that both the model and design work perfectly. Jer-Min Jou 周哲民 2000 學位論文 ; thesis 150 zh-TW |
collection |
NDLTD |
language |
zh-TW |
format |
Others
|
sources |
NDLTD |
description |
碩士 === 國立成功大學 === 電機工程學系 === 88 === More and more circuit can be put into one chip because of the continuing improvement on the production technique of semi-conductor. In order to short the developing time frame for System on a chip (SOC), how to systemize the description、 regulate the interface circuit among each intellectual property to get best design & connect each IP to complete the design of entire system chip has become a very important & disturbing subject for designers. Each connecting component has its own feature, and sometimes this could be very complicated. Main topic of this report is to find out how to clearly express & regulate system chip on the interface circuit in order to design an effective circuit to integrate every connecting component. We have provided the following solutions for description & regulation of interface circuit and problem for effective design.
First, we’ve analyzed the data transaction behavior among each component in every level and submit a description framework for a systemized level data transaction behavior. This structure can catch the data transaction behavior inside a system completely in a systemized description way under different levels. It can also allow the designers to have fully control of regulations for data transmitting behavior to increase the rate for successful chip integration design. The whole structure can be divided into four levels in order to describe this kind of behavior: algorithm level, functional level, virtual component level & state transition level.
Secondly, we use this structure to complete level design of interface circuit quickly by analyzing behavior features of data transaction among components in every system, building a corresponding triple interface design model, modifying each level’s necessary design features. The hierarchical interface design models we proposed are: abstract interface design model, virtual component interface design model, and state-level interface circuit design model. In this model, abstract interface design model is used to catch system’s data transaction characteristic in application and function level. Virtual component interface design model is used to describe both software and hardware’s abstract data transmission features in the system that is not related with the type of interface circuit to use. State-level interface circuit design model is used to identify the necessity of interface circuit and to design the whole circuit.
Finally, we develop a new and perfect interface design and practical method based on above mentioned multi-level data transmission structure and design model to analyze different circuit application principals. It allows us not only to describe and fulfill interface circuit of abstract data transmission behavior but also to systemize all the solutions for incompatible problems between connecting components and standardize design templates. The two advantages can work out the design problems on different levels. Take MPEG II video decoding system as an example, we’ve applied the multi-level circuit design method, model and description structure that we developed to complete the four interface circuit design among each component. The result shows that both the model and design work perfectly.
|
author2 |
Jer-Min Jou |
author_facet |
Jer-Min Jou Hsiao-cheng Wang 王效誠 |
author |
Hsiao-cheng Wang 王效誠 |
spellingShingle |
Hsiao-cheng Wang 王效誠 Methodology of Hierarchical Interface Design and Modeling - A case study for MPEG-2 video decoding |
author_sort |
Hsiao-cheng Wang |
title |
Methodology of Hierarchical Interface Design and Modeling - A case study for MPEG-2 video decoding |
title_short |
Methodology of Hierarchical Interface Design and Modeling - A case study for MPEG-2 video decoding |
title_full |
Methodology of Hierarchical Interface Design and Modeling - A case study for MPEG-2 video decoding |
title_fullStr |
Methodology of Hierarchical Interface Design and Modeling - A case study for MPEG-2 video decoding |
title_full_unstemmed |
Methodology of Hierarchical Interface Design and Modeling - A case study for MPEG-2 video decoding |
title_sort |
methodology of hierarchical interface design and modeling - a case study for mpeg-2 video decoding |
publishDate |
2000 |
url |
http://ndltd.ncl.edu.tw/handle/12587986923214656824 |
work_keys_str_mv |
AT hsiaochengwang methodologyofhierarchicalinterfacedesignandmodelingacasestudyformpeg2videodecoding AT wángxiàochéng methodologyofhierarchicalinterfacedesignandmodelingacasestudyformpeg2videodecoding AT hsiaochengwang jiēcéngshìjièmiàndiànlùmóxíngyǔshèjìfǎzézhīyánjiūyǐmpeg2shìxùnjiěmǎqìwèilì AT wángxiàochéng jiēcéngshìjièmiàndiànlùmóxíngyǔshèjìfǎzézhīyánjiūyǐmpeg2shìxùnjiěmǎqìwèilì |
_version_ |
1716834924862898176 |