| Summary: | 碩士 === 國立成功大學 === 電機工程學系 === 88 === ABSTRACT
In this paper, we present a VLSI design for adaptive multi-symbol arithmetic coding based on the analysis of the arithmetic coding parameters. These parameters include the binary and multi-symbol, the Markov model, the weighted history model, and the 2-dimensional state model etc. A new probability model scheme is then proposed, which provides more precise estimation of the symbol probability and uses less word length for Markov model memory, arithmetic units and registers. Besides, all the division operations are replaced by only one multiplication operation at the beginning of each coding process using a 121*12 bits ROM, and the difference of compression ratio compared to software division is less than 0.5%.
A binary searching architecture for decoding is also presented, it searches the decoded symbol from 256 ones. The normalization process is partitioned into two parts and then pipelined efficiently. One is the parallel execution part; the other is not on the critical path, so that it can be done sequentially with less hardware. The decoding algorithm above is then implemented into a VLSI chip by using the high level synthesis design methodology based on a 0.35mm CMOS technology. The resulting chip occupies a silicon area of about 25 mm2, yielding a compression rate of 4.44 Mbits/sec with a clock rate of 33 MHz.
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