| Summary: | 碩士 === 國立中興大學 === 資訊科學研究所 === 88 === As the IC（Integrated Circuit） industry continuously increases the number of transistors in a chip, the SOC（System On a Chip） finally becomes a reality. At the some time, the testing cost of a chip increases as well, so that DFT（Design for Testability） features become affective for all VLSI. Among those DFT techinques, BIST/BISR（Built-In Self-Test / Built-In Self-Repair）is the one which most effectively reduces the test cost, but the conventional BISR designs would also have the disadvantages of increasing area overhead and decreasing of circuit speed.
In the thesis we will introduce the method of Switch Array. It is proposed to substitute conventional compare module in BISR. With this method, the circuit speed penalty nearly negligible in CUT(Circuit Under Test) with BISR. Therefore The BISR in SOC could efficient test and repair embedded memories, hence the test is effectively reduced.
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