A VLSI Implementation of A Multicasting Shared Buffer for QoS Multimedia Networks

• Main Authors: Chen-Wei Hsu, 許辰維
• Other Authors: Yi-wen Wang
• Format: Others
• Language: zh-TW
• Published: 2000
• Online Access: http://ndltd.ncl.edu.tw/handle/70019837557618999932

碩士 === 逢甲大學 === 資訊工程學系 === 88 === In this thesis, a multicasting shared buffer switch architecture was proposed. The ATM switch can provide every traffic source with different traffic Quality of Service (QoS), and control each of them in real time according to its traffic QoS parameters and keep high throughput. In order to guarantee every traffic source''s QoS, each individual traffic source maintains a separate Link-List. The maximum flexibility and controllability of Link-List can be obtained. The proposed architecture utilizes share-buffering scheme to control the shared-buffer space, so as to decrease cell loss. This thesis improves the disadvantage of the waste of shared space caused by building a Link-List and develops a multicasting switch to provide point-to-multipoint communications. We implement and verify the structure via VHDL and C. The FPGA prototype implementation of our architecture can achieve 2.21G b/s.