| Summary: | 碩士 === 中原大學 === 資訊工程學系 === 88 === The field programmable gate array (FPGA) is a relatively new technology in VLSI designs. One of the important steps in the design flow of FPGAs is technology mapping. For lookup table (LUT) based FPGAs, technology mapping is the process of transforming the given circuit into an equivalent one that consists of only LUTs.
In this thesis, we consider the problem of LUT-based FPGA technology mapping for power minimization in combinational circuits. The problem has been proved to be NP-hard, and hence we present an efficient heuristic algorithm for it. The main idea of our algorithm is to exploit the “cut enumeration” technique to generate the set of all possible mapping solutions for the sub-circuit rooted at each node. However, for both run time and memory space consideration, only a fixed-number of possibly best solutions are selected and stored by our algorithm. To facilitate the selection process, a novel method that correctly calculates the estimated power consumption for each mapped sub-circuit is developed.
Our algorithm has been implemented in C language, and tested on 15 MCNC benchmark circuit. The experimental results indicate that our algorithm reduces the average power consumption by up to 14.18%, and the average number of LUTs by up to 6.99% over a previously existing method.
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