Module Placement with Boundary Constraints Using the Sequence-Pair Representation
碩士 === 中原大學 === 資訊工程學系 === 88 === Module placement is one of the important steps in VLSI physical design. It is to place a set of modules onto the chip such that without violating any given constraint (such as the constraint that disallows two modules to overlap) the total chip area (and/or the tota...
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ndltd-TW-088CYCU03920022015-10-13T11:53:30Z http://ndltd.ncl.edu.tw/handle/53407657480145874227 Module Placement with Boundary Constraints Using the Sequence-Pair Representation 以一對順序表示具邊界限制之超大型積體電路模組放置 Jian-Bang Lai 賴建邦 碩士 中原大學 資訊工程學系 88 Module placement is one of the important steps in VLSI physical design. It is to place a set of modules onto the chip such that without violating any given constraint (such as the constraint that disallows two modules to overlap) the total chip area (and/or the total wire length) is minimized. In this thesis, we study the boundary-constrained module placement problem where all the modules are hard and have the rectangular shape, and some of them must be placed along the pre-specified boundaries of the chip. We present a simulated annealing based method, which represents a placement topology by a sequence-pair, to solve the problem. We first prove a sufficient and necessary condition for a sequence-pair to be feasible. Based on the condition, we develop a polynomial-time method to transform a sequence-pair into a feasible one. The transformation method is then incorporated into our simulated annealing based module placement algorithm to help find a possibly best placement. Consequently our module placement algorithm ensures to generate a feasible placement, which indeed is a major advantage of our algorithm. Our algorithm has been implemented, and its effectiveness is supported by the encouraging experimental results. Ting-Chi Wang 王廷基 2000 學位論文 ; thesis 70 en_US |
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碩士 === 中原大學 === 資訊工程學系 === 88 === Module placement is one of the important steps in VLSI physical design. It is to place a set of modules onto the chip such that without violating any given constraint (such as the constraint that disallows two modules to overlap) the total chip area (and/or the total wire length) is minimized.
In this thesis, we study the boundary-constrained module placement problem where all the modules are hard and have the rectangular shape, and some of them must be placed along the pre-specified boundaries of the chip. We present a simulated annealing based method, which represents a placement topology by a sequence-pair, to solve the problem. We first prove a sufficient and necessary condition for a sequence-pair to be feasible. Based on the condition, we develop a polynomial-time method to transform a sequence-pair into a feasible one. The transformation method is then incorporated into our simulated annealing based module placement algorithm to help find a possibly best placement. Consequently our module placement algorithm ensures to generate a feasible placement, which indeed is a major advantage of our algorithm.
Our algorithm has been implemented, and its effectiveness is supported by the encouraging experimental results.
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Ting-Chi Wang |
author_facet |
Ting-Chi Wang Jian-Bang Lai 賴建邦 |
author |
Jian-Bang Lai 賴建邦 |
spellingShingle |
Jian-Bang Lai 賴建邦 Module Placement with Boundary Constraints Using the Sequence-Pair Representation |
author_sort |
Jian-Bang Lai |
title |
Module Placement with Boundary Constraints Using the Sequence-Pair Representation |
title_short |
Module Placement with Boundary Constraints Using the Sequence-Pair Representation |
title_full |
Module Placement with Boundary Constraints Using the Sequence-Pair Representation |
title_fullStr |
Module Placement with Boundary Constraints Using the Sequence-Pair Representation |
title_full_unstemmed |
Module Placement with Boundary Constraints Using the Sequence-Pair Representation |
title_sort |
module placement with boundary constraints using the sequence-pair representation |
publishDate |
2000 |
url |
http://ndltd.ncl.edu.tw/handle/53407657480145874227 |
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1716849544003584000 |