| Summary: | 碩士 === 中原大學 === 資訊工程學系 === 88 === Module placement is one of the important steps in VLSI physical design. It is to place a set of modules onto the chip such that without violating any given constraint (such as the constraint that disallows two modules to overlap) the total chip area (and/or the total wire length) is minimized.
In this thesis, we study the boundary-constrained module placement problem where all the modules are hard and have the rectangular shape, and some of them must be placed along the pre-specified boundaries of the chip. We present a simulated annealing based method, which represents a placement topology by a sequence-pair, to solve the problem. We first prove a sufficient and necessary condition for a sequence-pair to be feasible. Based on the condition, we develop a polynomial-time method to transform a sequence-pair into a feasible one. The transformation method is then incorporated into our simulated annealing based module placement algorithm to help find a possibly best placement. Consequently our module placement algorithm ensures to generate a feasible placement, which indeed is a major advantage of our algorithm.
Our algorithm has been implemented, and its effectiveness is supported by the encouraging experimental results.
|
|---|
