Test Strategy and Testability Analysis of Pipelined DSP
碩士 === 中華大學 === 電機工程學系碩士班 === 88 === This thesis describes a 24 bits programmable digital signal processor（DSP）that applys to communication, video, speech and image. This architecture of processor is a reduced instruction set computer（RISC）which has pipeline to improve the performance. Te...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/78398458115340927953 |