Fourth-Power Law Clock Recovery Using Phase-Locked Loop

• Main Authors: Yi-Bin Chu, 朱衣斌
• Other Authors: Thomas T. Fang
• Format: Others
• Language: en_US
• Published: 2000
• Online Access: http://ndltd.ncl.edu.tw/handle/42725627883660515555

碩士 === 國立中正大學 === 電機工程研究所 === 88 === Data communication systems require a regenerated clock to retrieve transmitted information. The recovered clock is contaminated by both the additive noise in the transmission channel paths and self-noise, which occurs because of the random nature of the data itself and of the action of the nonlinear device. If the signal has narrow bandwidth and high signal-to-noise ratio, self-noise is the predominant source of phase noise in the regenerated clock. The self-noise component that is in phase with the recovered clock plays a different role from the component that is in quadrature. Only the quadrature component necessarily contributes to time jitter of the recovered clock. In order to conserve signal bandwidth with ever-increasing amount of data to be transmitted at fixed frequency bandwidth allocation, it is proposed that the fourth-power law clock recovery scheme be used. Our scheme uses a prefilter centered at 1/4T and of a bandwidth not greater than 1/8T, where T is the symbol period. It was found that time jitter due to self-noise can be completely eliminated if signal is sent only during every other symbol periods. We will study the performance of the clock recovery scheme in which symbol phase is obtained through processing the received signal after it has passed through a prefilter and a fourth-power law device. The symbol error rates (SER) of various M-ary QAM signal data were simulated when a phase-locked loop was used at the receiver for clock recovery in conjunction with a fourth-power law processing. We found the self-noise dominates the error rates with a signal-to-noise ratio higher than 25 dB.