| Summary: | 碩士 === 國立中正大學 === 電機工程研究所 === 88 === Radar signal processing features large quantity of data and severe timing constraints. To this end, the hardware system must be very efficient to deal with successively incoming data. Thus, traditional radar signal processing systems are generally
implemented with dedicated and proprietary hardware to deal with these complex operations, like convolution, FFT, etc. Although this type of implementation offers high-performance solution, it faces some penalties. In recent years, with the advance of general-purpose digital signal processors (DSPs), more and more signal processing systems are implemented based on DSPs. In this thesis, we present an architecture for radar signal processing systems demanding computation-intensive capability based on general-purpose digital signal processors, discuss its advantages and disadvantages, and evaluate its performance. In our architecture, we exploit multistage
interconnection network (MIN) as a fast and parallel global interconnection network between the processors and the memories. We also explore the impact of a variety of
interconnection schemes on the overall system performance.
We present an analytical study to help the system designers make correct and efficient decisions when they design the system. The results show this architecture is feasible, efficient and cost-effective.
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