Hardware Design For ATM Based Access Transport System
博士 === 國立中正大學 === 電機工程研究所 === 88 === At the age of Internet, network equipment must have the capability to support broadband services. The Asynchronous Transfer Mode (ATM) Virtual Path (VP) based Add Drop Multiplexer (ADM) is designed for multiplexing ATM cells with all kinds of services....
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ndltd-TW-088CCU004420112015-10-13T11:50:28Z http://ndltd.ncl.edu.tw/handle/68624651803872886963 Hardware Design For ATM Based Access Transport System 基於非同步傳輸模式之介接傳送系統 Yih-Chang Lee 李益彰 博士 國立中正大學 電機工程研究所 88 At the age of Internet, network equipment must have the capability to support broadband services. The Asynchronous Transfer Mode (ATM) Virtual Path (VP) based Add Drop Multiplexer (ADM) is designed for multiplexing ATM cells with all kinds of services. ATM is a new transfer technology, which combines the advantages of circuit switching and flexibility of packet switching. It is possible for ATM to transmit almost all kinds of services. Similar to the architecture of SONET/SDH ADM, the ATM VP-based ADM is designed. It is more flexible in adding and dropping VP's without the time slot interchange (TSI) problem. With its capability of alarm and fault indication system to provide protection, the ATM VP-based ADM can be used in Self-healing Ring architecture. Different service adaptation functions can be realized according to the service provided in the access link, it is very suitable for access transport system. To use ATM as the backbone network of transmission, it must support existing circuit-switched services. For constant bit rate (CBR) service with delay constraint, ATM adaptation layer type 1 (AAL1) is used to transmit asynchronous digital signals from plesiochronous digital hierarchy (PDH). It is called circuit emulation to transport an asynchronous digital signal through ATM network. In order to meet the requirements of jitter and wander, the Synchronous Residual Time Stamp (SRTS) method is implemented. In the design, there are two high-speed 155.52 MHz STM-1/STS-3c optical link in the ATM ADM. It can add and drop up to 16 access units. The access unit for DS1/E1 circuit emulation lines is designed. Each can handle 4 channels of DS1/E1 tributaries. The timing generator unit provides the network synchronized clock and the system control unit is designed for control and management functions. The ATM ADM system is system integrated and tested. Kou-Tan Wu 吳國棟 2000 學位論文 ; thesis 92 en_US |
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博士 === 國立中正大學 === 電機工程研究所 === 88 === At the age of Internet, network equipment must have the capability to support broadband services. The Asynchronous Transfer Mode (ATM) Virtual Path (VP) based Add Drop Multiplexer (ADM) is designed for multiplexing ATM cells with all kinds of services. ATM is a new transfer technology, which combines the advantages of circuit switching and flexibility of packet switching. It is possible for ATM to transmit almost all kinds of services. Similar to the architecture of SONET/SDH ADM, the ATM VP-based ADM is designed. It is more flexible in adding and dropping VP's without the time slot interchange (TSI) problem. With its capability of alarm and fault indication system to provide protection, the ATM VP-based ADM can be used in Self-healing Ring architecture. Different service adaptation functions can be realized according to the service provided in the access link, it is very suitable for access transport system.
To use ATM as the backbone network of transmission, it must support existing circuit-switched services. For constant bit rate (CBR) service with delay constraint, ATM adaptation layer type 1 (AAL1) is used to transmit asynchronous digital signals from plesiochronous digital hierarchy (PDH). It is called circuit emulation to transport an asynchronous digital signal through ATM network. In order to meet the requirements of jitter and wander, the Synchronous Residual Time Stamp (SRTS) method is implemented.
In the design, there are two high-speed 155.52 MHz STM-1/STS-3c optical link in the ATM ADM. It can add and drop up to 16 access units. The access unit for DS1/E1 circuit emulation lines is designed. Each can handle 4 channels of DS1/E1 tributaries. The timing generator unit provides the network synchronized clock and the system control unit is designed for control and management functions. The ATM ADM system is system integrated and tested.
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author2 |
Kou-Tan Wu |
author_facet |
Kou-Tan Wu Yih-Chang Lee 李益彰 |
author |
Yih-Chang Lee 李益彰 |
spellingShingle |
Yih-Chang Lee 李益彰 Hardware Design For ATM Based Access Transport System |
author_sort |
Yih-Chang Lee |
title |
Hardware Design For ATM Based Access Transport System |
title_short |
Hardware Design For ATM Based Access Transport System |
title_full |
Hardware Design For ATM Based Access Transport System |
title_fullStr |
Hardware Design For ATM Based Access Transport System |
title_full_unstemmed |
Hardware Design For ATM Based Access Transport System |
title_sort |
hardware design for atm based access transport system |
publishDate |
2000 |
url |
http://ndltd.ncl.edu.tw/handle/68624651803872886963 |
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