| Summary: | 碩士 === 國立中正大學 === 資訊工程研究所 === 88 === With the rapidly development tread of processors, the performance demand is not any more an important constraint in the embedded system or the real-time system. Instead, the issue that to operate on a lower power dissipation level becomes more and more important especially for the battery-based system. When the system consumes lower power dissipation, the battery can have a longer lifetime. Evaluating the power dissipation on a system chip, we can observe that the cache consumes a huge part of power dissipation. And thus, to reduce the power dissipation in the cache becomes an important object in low power research topic.
In this paper, we present two cache architectures for reducing the L1 cache energy dissipation in embedded systems. The first cache architecture is call CoC, a caching on cache. The cache with CoC can reduce the access frequency at the word-line and bit-line that are the main power consumption components, in both tag and data array. In addition, we use the hierarchical address comparison (HAC) scheme to optimize the energy reduction and comparison time. Another architecture for reducing the cache power dissipation is that cache with dual voltage/3-stages pipelined. This cache can operate on the two modes: in either the normal mode or the low voltage mode. When the cache is operated in power save mode, the access operation is pipelining execution. By the instruction scheduling, we can reduce some stall time in the power save mode. And with the task scheduling, we achieve the better energy reduction by selecting part of tasks into power save mode.
Experimental results show that the CoC with HAC is practical in reducing energy dissipation about 40% in L1 cache and the comparison penalty in the CoC. Besides, the
dual voltage/pipelining cache can achieve about 10.74% energy reduction.
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