On the Design and Test of Algorithmic Switched-Current A/D Converter

• Main Authors: Hsiao-Hsing Chou, 周孝興
• Other Authors: Ming-Der Shieh
• Format: Others
• Language: zh-TW
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/56743532262233429276

碩士 === 國立雲林科技大學 === 電子工程與資訊工程技術研究所 === 87 === With the evolution of system integration and portable systems, the demands of incorporating both analog and digital electronics, the so-called mixed-signal circuits, become a practical and inevitable tendency. The integrated analog and digital circuits can provide the performance improvement as well as reducing the board size and cost. Unfortunately, the combination of analog and digital electronics in denser and smaller packaging is creating a very difficult situation to access, test and verify the analog behavior. In this thesis, we focus on the fault-oriented tests instead of specification-based tests for mixed-signal circuits based on realistic VLSI technology. The aim of this thesis is to go through the fault-oriented test procedure, explore the corresponding fault models, and develop test schemes and strategies for switched-current A/D converter circuit based on the 0.6 um 1P3M process supported by TSMC. The reason we choose the switched-current implementation style is two fold: First, the A/D and D/A converters, occupying a small portion of the total chip area, is the most common analog building blocks in the mixed-signal circuits/systems. They can be implemented using switched-current techniques that are compliant to the digital process. Secondly, the selected switched-current ADC can be used to verify the experimental results and dynamic current copier can be also used for testing purpose such that it provides the potential for DFT development. In this thesis, we have successfully designed a high-resolution algorithmic switched-current A/D converter, which is easily testable based on the following fault models: the stuck-fault and bridging-fault models. In our design, only two test patterns are needed for fault detection and it is possible to add three more test patterns for the purpose of fault location. In addition, the layout rules towards avoiding hard-to-detect faults in mixed-signal circuits are carefully examined to improve the testability measure and ease the test. In consequence, our results can provide a deep insight on the design and test of algorithmic switched-current A/D converter and can be used as a basis of future research for other types of switched-current circuits.