| Summary: | 碩士 === 國立雲林科技大學 === 電子工程與資訊工程技術研究所 === 87 === In this thesis, a novel bit serial computing scheme based on signed-digit number system was first proposed. It features a MSB first computing style and provides a generic way to exploit computing concurrency between successive data. Via bit-level pipelining, high throughput rate design can the be achieved. The scheme is particularly useful in implementing recursive computing algorithms where tight data dependency has limited the computing concurrency available. Based on the proposed scheme, an all digital QAM channel equalizer was designed. The nonlinear feedback path formed by the decision feedback equalizer (DFE) and the slicer in the QAM channel equalizer has traditionally been the performance bottleneck. Conventional bit parallel approach requires dramatic hardware to achieve the desired baud rate. In contrast, our design features a scalable, low circuit complexity yet high throughput design. A VLSI implementation in TSMC 0.6um CMOS process was also presented. For a 64 QAM channel equalizer with 8-tap DFE and FFE, the design can achieve 110MHz clocking rate and 15.7M baud symbol rate in 18.3 mm2 chip die size.
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