A Simulation Study of the MAC Protocol for Wireless ATM

• Main Authors: Hsieh-Chang Huang, 黃謝璋
• Other Authors: Chien-Hua Chen
• Format: Others
• Language: en_US
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/25922742070460615790

碩士 === 大同工學院 === 資訊工程研究所 === 87 === Abstract Today, wireless network is more and more popular. Many people are researching this technology. The concept of wireless ATM is now being actively considered as a potential framework for next-generation wireless communication networks capable of supporting integrated multimedia services with different QoS requirements. Several key subsystem design issues for wired ATM and wireless networks need to be readdressed in the scope of the wireless ATM. One of the main key subsystem issues is the development of the appropriate medium access control (MAC) protocol, which has the capability to extend the statistical multiplexing of the wired ATM network into the wireless medium. In this thesis, we address the problem of the suitable MAC protocol for the specification of a wireless ATM network and outline the design objectives. The medium access control (MAC) protocol and the underlying traffic scheduling algorithm developed within project Magic WAND (Wireless ATM Network Demonstrator) are presented. Magic WAND is investigating wireless ATM technology for customer premises networks in the framework of the Advanced Communications Technologies and Services (ACTS) program funded by the European Union. The MAC protocol, known as MASCARA (Mobile Access Scheme Based on Contention and Reservation for ATM), is a hub-based, adaptive TDMA scheme which combines reservation and contention-based access methods to provide multiple access efficiency and quality-of-service guarantees to wireless ATM terminal connections sharing a common radio channel. The traffic-scheduling algorithm is delay-oriented to meet the requirements of the various traffic classes defined by the ATM architecture. The Block Oriented Network Simulator (BONeS) DESIGNER provides a graphical environment for modeling and discrete event simulation of computer and communication networks, discrete and computer systems, and computer architectures. DESIGNER uses a hierarchical data flow block diagram model paradigm, which provides for definition of data structures that flow between blocks. This modeling paradigm provides sufficient flexibility to model and simulate a broad range of discrete-event systems, including computer networks and distributed processing systems. We simulate MASCARA with BONeS DESIGNER in this thesis.