Design and Application of Smart Photonic Logic Gates

• Main Authors: Jiang-Duh Fang, 方江渡
• Other Authors: Wen-Ching Chang
• Format: Others
• Language: en_US
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/99112188590933734059

碩士 === 淡江大學 === 電機工程學系 === 87 === A novel smart photonic logic gate system, including NOT, AND, OR, XOR gates, direct type OR with multiple inputs has been proposed for the first time. It takes many advantages of the linear device operation, facility of the multiple inputs, and being easy to realize logic functions as compared to the conventional photonic logic gate systems. The main components on these smart photonic logic gates includes the integrated optical waveguide directional couplers, optoelectronic (OE) devices, erbium-doped fiber amplifiers (EDFAs), 50/50 optical couplers, delay lines, and a built-in DFB laser. The design consideration of the waveguide directional couplers, such as switching voltage, electrode gap, coupling length, operating wavelength, would be studied in detail in this thesis. In chapter 1, the substrate materials of directional couplers would be concentrated on LiNbO3 technologies because of its low propagation loss and high electrooptic coefficients. In chapter 2, the components of smart photonic logic gates would be designed and then integrated by using semiconductor technologies such as gallium arsenide, indium phosphide. The operating characteristics of the optoelectronic devices which include UTC-PD, PIN/HBT, and MSM-PD, would be also investigated in order to integrate the whole components in the photonic logic gates. In chapter 3, the characteristics of the photonic logic gate systems, such as guided mode (TE or TM), operating wavelength, such as switching voltages, propagation and dielectric losses, crosstalk, will be investigated by using the two and three dimensional beam propagation method (BPM). In chapter 4, the operation limitation of the smart photonic logic gates, such as operating frequency, the numbers of maximum and optimal inputs, the max numbers of cascade stages, and device dimension, would be also considered and proved to be informative. Moreover, the architecture and their characteristics of the smart photonic ring oscillator, left and right shift register, SR, JK, D type, and T type flip-flop would be studied. In chapter 5, the major work would be focused on the application of the smart photonic logic gates on the WDM network. For example, the jitter detection on hardware technology and CRC-32 data correction are expected to increase the performance in the WDM network. In the near future, it is believed that this smart photonic logic gates system should be of great interest in the design of wideband optical communication network.