Chip Design and Implementation for High Speed ATM Adaptaion Layer Type 1 (AAL-1)

• Main Authors: Kao Chih-Hong, 高誌鴻
• Other Authors: Kuo Sy-Yen
• Format: Others
• Language: en_US
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/63569677159797841528

碩士 === 國立臺灣大學 === 電機工程學研究所 === 87 === This thesis describes a design of the ATM Adaptation Layer type 1(AAL1) chip for ATM network. The AAL1 segmentation and reassembly(SAR) chip are designed and implemented by the 0.6um SPTM CMOS process. The cell header of SAR-PDU is generated and processed in the chip and the SAR-PDU payload is stored in Compass two-port RAM devices. The robust SN algorithm which reassembles the received cells, is used for sequence number processing. A method to recover the source clock, called Synchronous Residual Time Stamp(SRTS), is designed and implemented in this system. For convenience testing, we increase 8 pins and Test Data Loop(TDL) when AAL1 chip designed, and this hardware overhead could make observation of internal block state more easy. The AAL1 chip which contains 126k CMOS transistors, is implemented using 0.6um Single Polysilicon Triple Metal(SPTM) CMOS process and the Compass standard cell library. The chip area is 4360um*4360um and is packaged in a 100-pin CQFP. The operating frequency is 77.76MHz, which supports to 622.08MHz ATM network.