A Circuit Design for Low-Voltage VLSI Fe-RAM
碩士 === 國立臺灣大學 === 電機工程學研究所 === 87 === In thesis, a ferroelectric capacitor macro model and a low voltage VLSI Fe-RAM circuit has been proposed. The model mainly consists of four linear capacitors, corresponding to the two different polarization states of a ferroelectric capacitor. In the model, the...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1999
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| Online Access: | http://ndltd.ncl.edu.tw/handle/95996933939071222087 |