The Design and Realization of the FSK Receiver IF Circuit
碩士 === 國立臺灣大學 === 電機工程學研究所 === 87 === In this thesis, an FSK superheterodyne receiver including downconverting mixer, limiting amplifier, RSSI and PLL is realized. This system operates in 0/3.3V, RF = 110MHz, IF = 10.7MHz, FSK bit rate = 64Kb/s, and frequency deviation =75KHz. The chip has been fabr...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1999
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| Online Access: | http://ndltd.ncl.edu.tw/handle/21942023769258056023 |