The Design and Implementation of a 10-bit Pipelined Analog-to-Digital Converter

碩士 === 國立臺灣大學 === 電機工程學研究所 === 87 === In this thesis, a 10 bit, 20Msample/s pipelined analog-to-digital converter for video-rate applications is designed. The 1.5b/stage architecture with digital correction is adopted in this pipelined ADC. It consists of 9 stages in which only 19 compa...

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Main Authors: Chih-Kai Kang, 康智凱
Other Authors: Shen-Iuan Liu
Format: Others
Language:en_US
Published: 1999
Online Access:http://ndltd.ncl.edu.tw/handle/43559116988636945844
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spelling ndltd-TW-087NTU004420472016-02-01T04:12:41Z http://ndltd.ncl.edu.tw/handle/43559116988636945844 The Design and Implementation of a 10-bit Pipelined Analog-to-Digital Converter 10位元導管式類比數位轉換器之設計與實作 Chih-Kai Kang 康智凱 碩士 國立臺灣大學 電機工程學研究所 87 In this thesis, a 10 bit, 20Msample/s pipelined analog-to-digital converter for video-rate applications is designed. The 1.5b/stage architecture with digital correction is adopted in this pipelined ADC. It consists of 9 stages in which only 19 comparators and 9 low power operational amplifiers are needed. So low power and low cost can be achieved. For low power operation, a 3V, high gain op-amp with power dissipation about 3.1mW is designed. It is used in the sample-and hold (S/H) circuit and the multiplying D/A converter (MDAC) which is the key block in the developed pipelined ADC. Fully-differential structure is used to reduce 2nd order harmonic distortion. Signal-to-noise ratio is 52.7dB for whole-chip simulation with 1.5MHz input sampled at 20 Msample/s. A capacitor re-arrangement technique for MDAC is also proposed. The new architecture provides superior monotonicity to that of conventional pipelined converters is presented. The prototype A/D converter has been fabricated in a double-poly double metal (DPDM) 0.35um CMOS technology. Shen-Iuan Liu 劉深淵 1999 學位論文 ; thesis 78 en_US
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description 碩士 === 國立臺灣大學 === 電機工程學研究所 === 87 === In this thesis, a 10 bit, 20Msample/s pipelined analog-to-digital converter for video-rate applications is designed. The 1.5b/stage architecture with digital correction is adopted in this pipelined ADC. It consists of 9 stages in which only 19 comparators and 9 low power operational amplifiers are needed. So low power and low cost can be achieved. For low power operation, a 3V, high gain op-amp with power dissipation about 3.1mW is designed. It is used in the sample-and hold (S/H) circuit and the multiplying D/A converter (MDAC) which is the key block in the developed pipelined ADC. Fully-differential structure is used to reduce 2nd order harmonic distortion. Signal-to-noise ratio is 52.7dB for whole-chip simulation with 1.5MHz input sampled at 20 Msample/s. A capacitor re-arrangement technique for MDAC is also proposed. The new architecture provides superior monotonicity to that of conventional pipelined converters is presented. The prototype A/D converter has been fabricated in a double-poly double metal (DPDM) 0.35um CMOS technology.
author2 Shen-Iuan Liu
author_facet Shen-Iuan Liu
Chih-Kai Kang
康智凱
author Chih-Kai Kang
康智凱
spellingShingle Chih-Kai Kang
康智凱
The Design and Implementation of a 10-bit Pipelined Analog-to-Digital Converter
author_sort Chih-Kai Kang
title The Design and Implementation of a 10-bit Pipelined Analog-to-Digital Converter
title_short The Design and Implementation of a 10-bit Pipelined Analog-to-Digital Converter
title_full The Design and Implementation of a 10-bit Pipelined Analog-to-Digital Converter
title_fullStr The Design and Implementation of a 10-bit Pipelined Analog-to-Digital Converter
title_full_unstemmed The Design and Implementation of a 10-bit Pipelined Analog-to-Digital Converter
title_sort design and implementation of a 10-bit pipelined analog-to-digital converter
publishDate 1999
url http://ndltd.ncl.edu.tw/handle/43559116988636945844
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