The Design and Implementation of a 10-bit Pipelined Analog-to-Digital Converter
碩士 === 國立臺灣大學 === 電機工程學研究所 === 87 === In this thesis, a 10 bit, 20Msample/s pipelined analog-to-digital converter for video-rate applications is designed. The 1.5b/stage architecture with digital correction is adopted in this pipelined ADC. It consists of 9 stages in which only 19 compa...
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| Format: | Others |
| Language: | en_US |
| Published: |
1999
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| Online Access: | http://ndltd.ncl.edu.tw/handle/43559116988636945844 |
| Summary: | 碩士 === 國立臺灣大學 === 電機工程學研究所 === 87 === In this thesis, a 10 bit, 20Msample/s pipelined analog-to-digital converter for video-rate applications is designed. The 1.5b/stage architecture with digital correction is adopted in this pipelined ADC. It consists of 9 stages in which only 19 comparators and 9 low power operational amplifiers are needed. So low power and low cost can be achieved. For low power operation, a 3V, high gain op-amp with power dissipation about 3.1mW is designed. It is used in the sample-and hold (S/H) circuit and the multiplying D/A converter (MDAC) which is the key block in the developed pipelined ADC. Fully-differential structure is used to reduce 2nd order harmonic distortion. Signal-to-noise ratio is 52.7dB for whole-chip simulation with 1.5MHz input sampled at 20 Msample/s. A capacitor re-arrangement technique for MDAC is also proposed. The new architecture provides superior monotonicity to that of conventional pipelined converters is presented. The prototype A/D converter has been fabricated in a double-poly double metal (DPDM) 0.35um CMOS technology.
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