Design and Implementation of an Inverse Multiplexing Chip for ATM

• Main Authors: Chiu Fu Hsuan, 邱富萱
• Other Authors: Sy-Yen Kuo
• Format: Others
• Language: en_US
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/74150933598982850119

碩士 === 國立臺灣大學 === 電機工程學研究所 === 87 === This thesis describes the design and implementation of a chip that sits between an ATM Layer device and multiple Physical (PHY) Layer devices to allow the transport of a single ATM stream onto multiple, independent lower speed ATM streams. To facilitate the system prototyping, we choose Programmable Logic Device (PLD) in our implementation. The MAX+PLUSII development software from Altera Ltd. provides us a simple design environment to design the prototype chip. Both PHY and ATM layer components are needed along with an IMA layer to provide a complete IMA system. The IMA chip has been designed to be compatible with a 8-port IMA architecture. The resultant Altera device EPM9560AQFP240 has 240pins.