The Design and Realization of Folding and Interpolating A/D Converter
碩士 === 國立臺灣大學 === 電機工程學研究所 === 87 === A 3v 10-bit 20MS/s Folding and Interpolating ADC has been designed and fabricated in Sharp 0.35um DPDM CMOS technology In this thesis. The measurement is under 3v power supply and 20MS/s. The results are in the following: ENOB 6-bit、DNL -1LSB~+1.5LSB 、INL -8.1LS...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
1999
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| Online Access: | http://ndltd.ncl.edu.tw/handle/21789207547212085730 |
| Summary: | 碩士 === 國立臺灣大學 === 電機工程學研究所 === 87 === A 3v 10-bit 20MS/s Folding and Interpolating ADC has been designed and fabricated in Sharp 0.35um DPDM CMOS technology In this thesis. The measurement is under 3v power supply and 20MS/s. The results are in the following: ENOB 6-bit、DNL -1LSB~+1.5LSB 、INL -8.1LSB~+8.1LSB and power 181mW. According to the measurement results, a new offset cancellation technique which is used to reduce nonlinear errors and increase 2-3 bits is proposed.
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