Design and Implementation of a FLEX Decoder for Pagers

• Main Authors: PENG, Chi-yuan, 彭起元
• Other Authors: Hen-Wai Tsao
• Format: Others
• Language: zh-TW
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/48815815561440292528

碩士 === 國立臺灣大學 === 電信工程學研究所 === 87 === With the flourishing progress of technology, a fusion of computers, consuming products, and communications has opened a brand-new page for pagers. Experts predict that in the near future pagers will become a versatile communication device. Just by simple operation, consumers will conveniently possess integrated services in paging, faxing, voice, and even financial transaction. FLEX is a new generation paging system proposed by Motorola in 1993 and has already attained over 70% market share nowadays. Therefore, it has very high commercial value and is quite worth further development. In this thesis, a FLEX decoder as a heart component in a FLEX pager is successfully designed and implemented into an FPGA chip. A new idea with simplified decoding functions is realized to have our decoder more cost-effective than any commercially available one. Many unique and creative design algorithms for our decoder circuit are detailed in this thesis to improve the entire system performance or to reduce the chip area. These delicate designs include noise processing, timing recovery, error compatibility for synchronization detection, simplified memory control for deinterleaving, and more efficient structure for error correction. Moreover, to testify the reliability and robustness of our decoder circuit, much more stringent glitches, Doppler effect, and burst noise are purposely added in our simulation and FPGA verification and even a much faster system clock of 50MHz instead of the normal one, 76.8KHz, is utilized to verify our circuit. Actually, these actions often drive our design to take as many ill effects into account as possible and make our decoder more realistic in real operations. The physical level design is first coded with Verilog, and then synthesized via Synopsys, complied and simulated by Max+Plus2. Finally, it is programmed into an Altera FPGA chip for verification.