A Study of Trap-Assisted Tunneling Gate Current in PMOSFET's with Sub-3nm Gate Oxide

• Main Authors: Cheng-Jye Liu, 劉承傑
• Other Authors: Charles Ching-Hsiang Hsu
• Format: Others
• Language: zh-TW
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/90020135281191920546

碩士 === 國立清華大學 === 電機工程學系 === 87 === In order to increase performance and reduce production cost, CMOS scaling is an inevitable trend. As the channel length decreases, thin oxide is required to retain the gate controllability. The advantages of ultra-thin oxide devices include large channel current, short channel effect suppression, low voltage operation, low power consumption, high circuit speed. But many problems may arises, such as decrease of breakdown voltage and mobility, poly-gate depletion enhancement and significant leakage current. Larger gate leakage current might become the major concern of CMOS device design. But gate current in ultra-thin oxide device couldn't modeled by conventional FN or direct tunneling current model. Several modified gate current model appears recently, trap-assisted tunneling( TAT ) is one of them. In this study, a larger gate current produced by band-to-band tunneling in PMOSFET with sub-3nm gate oxide is observed. In addition to analyzing gate current mechanisms in PMOSFET's with sub-3nm gate oxide by TAT model, a new gate current model named TAB( Trap-Assisted Band-to-Band Tunneling Induced Gate Current ) will be proposed. This model could explain the gate current near zero gate bias in PMOSFET's with sub-3nm gate oxide. Gate currents of PMOSFET's with the same oxide thickness but different oxidation processes could also be modeled through TAB model very well.