Analysis of Si Substrate Coupling Noise

• Main Authors: Yi-Ching Li, 李宜靜
• Other Authors: Jeng Gong
• Format: Others
• Language: en_US
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/61553270303959792262

碩士 === 國立清華大學 === 電機工程學系 === 87 === In large mixed-signal circuits, digitally injected substrate noise has recently become a key problem for circuit designers. However, there is no published procedure that let circuit designers to model the substrate coupling noise of analog circuit in large mixed-signal designs effectively. In order to predict the effect of substrate coupling noise, the use of the simple model is presented. The behavior of substrate coupling noise is observed by simulating and experimenting with the simple model. Analysis of substrate coupling noise of different distances between analog and digital circuits and the use of guard rings is also performed. Industry aimed at integrating higher levels of circuit functionality and fabricated the analog and digital circuit on the same die. This combination is required for both high-speed digital circuits and high precision analog circuits. Very fast switching transients in digital circuits may introduce an unacceptable level of noise in high precision analog sections. In large mixed-signal circuits, digitally injected substrate noise has recently become a key problem for circuit designers. However, there is no published procedure that let circuit designers to model the substrate coupling noise of analog circuit in large mixed-signal designs effectively. Substrate modeling for circuit simulation has become the focus of many researches in recent years. Substrate coupling noise is a serious problem and a limitation in mixed-signal circuit, various guard-ring techniques have been proposed to suppress the noise. The guard rings result in low-impedance node. In this work we developed simulation model and some experimental techniques . We make an effort to attain new models for practical simulations. A two-dimensional device simulator MEDICI and circuit simulator HSPICE have been used to obtain noise trends. Experimental results have been obtained through the design of 0.6 um CMOS technology with different conditions. Analysis of substrate coupling noise of different distances between analog and digital circuits and the use of guard rings is also performed.