| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 87 === We investigate the issues of design-for-testability, diagnosis and fault tolerance schemes for fast Fourier transform (FFT) networks in this thesis. A novel C-testable technique for FFT
butterfly networks is proposed. Only 18 test patterns are required to achieve 100% coverage of combinational single cell faults and interconnect stuck-at faults for the FFT network.
Moreover, the undetected stuck-at and stuck-open faults of interconnects in normal operation can be detected with additional two test patterns. Assume that the three global lines of the basic cells are fault free, our method can concurrently detect and locate multiple cell faults
and multiple faulty rows, respectively. A fault tolerant design for the FFT network also has been proposed. Compared with previous results, our approach has higher reliability and
lower hardware overhead---only three spare bit-level cells are needed for repairing a faulty row in the multiply-subtractor-add (MSA) module, and special cell design is not required to implement the reconfiguration scheme. The hardware overhead is low---about 4% for 16-bit numbers regardless of the FFT network size. M-testability conditions and technique based on double MSA (DMSA) module for FFT
networks are then proposed. Our approach can achieve 100% fault coverage with considerably less test vectors. By a new diagnosis approach with exchanging and blocking
fault propagation paths, a faulty DMSA module can be located by a two-phase algorithm. Compared with the previous schemes, our approach can reduce the diagnosis complexity from O(N) to O(1). For both testing and diagnosis, the hardware overhead for our approach is low, which is about 0:48% for 16-bit numbers regardless of the FFT network size.
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