An Access Stream Reordering Chip for Maximizing SDRAM Throughput
碩士 === 國立清華大學 === 資訊工程學系 === 87 === SDRAM is popular and has features such as synchronous operation, multiple internal banks, and burst mode operation. These features make the throughput dependent on the access sequence. We examine the dependence and propose a memory controller for maximi...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1999
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/60924504127881824444 |
| Summary: | 碩士 === 國立清華大學 === 資訊工程學系 === 87 === SDRAM is popular and has features such as synchronous operation, multiple internal banks, and burst mode operation. These features make the throughput dependent on the access sequence. We examine the dependence and propose a memory controller for maximizing the system throughput by buffering and reordering a window of access stream. This controller can be used in such applications as network switch buffers in which the throughput is more important than the turnaround time of each individual access. A VLSI chip has been implemented.
|
|---|