| Summary: | 碩士 === 國立清華大學 === 資訊工程學系 === 87 === We propose an efficient hardware architecture for the Blowfish encryption/ decryption algorithm. The architecture can achieve high-speed data transfer up to 4 bits per clock, which is 9 times faster than a Pentium. Although the Blowfish algorithm consists of a loop iterating 16 rounds and the block size is 64 bits, the I/O of the proposed architecture is reduced to 4 bits, and the I/O port is serialized. By applying operator-rescheduling method, the critical path delay is improved by 21.7%. Besides, Design for Testability (DFT) is also considered. To prove the correctness of the proposed architecture, we have successfully implemented it using Compass cell library targeted at a 0.6 mm TSMC SPTM CMOS process. The die size is 5.7x6.1 mm2 and the maximum frequency is 50MHz. This Blowfish cipher chip can be applied to such areas as a security system for high-speed networks.
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