| Summary: | 碩士 === 國立東華大學 === 資訊工程學系 === 87 === In the past few years, all kinds of portable systems, such as cellular phones, laptop computers, personal digital assistants, and wireless communication systems etc., are getting more and more popular. Due to the popularity of portable systems as well as the concerns of environmental and cost issues, low power design has become a very important research subject. In the area of VLSI design, the consideration of low power is now as important as that of circuit performance and chip area.
In an integrated circuit, load capacitance, active factor and supply voltage are three major sources for power dissipation. Designers can solve power dissipation problems in different design levels based on the above power dissipation factors, including architecture level, gate level, and circuit level. Basically, power dissipation is in proportion to load capacitance. Furthermore, the load capacitance from off-chip buses is about thousands of that from internal nodes. Hence, the power dissipation from buses is about thousands of that from internal nodes. If we effectively cut down the active factor of the bus, we can then reduce power dissipation significantly.
In this thesis, we propose two methods for encoding an external address bus which lower its switching activity. By using the characteristics of high degree of address sequentiality, the energy is decreased. In our experiments, the address traces are generated from a SUN SPARC machine running some benchmark programs. We find that with our encoding scheme the bus activity can be reduced up to 70% over the original address trace.
While our encoding schemes reduce switching activity significantly, the increase of the circuit complexity is limited. We have used the computer aided design tools to synthesize our design, and calculate the gate counts. It is shown that the circuit complexity of our schemes are comparative to other schemes.
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