Versatile Tree-Based Routing for Regular Interconnection Networks

• Main Authors: Ding-yi Lin, 林定一
• Other Authors: Hsin-Chou Chi
• Format: Others
• Language: zh-TW
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/18280530131823544486

碩士 === 國立東華大學 === 資訊工程學系 === 87 === Multiprocessors are usually used in application areas requiring highly parallel computing such as scientific computing. A high-performance multiprocessor typically consists of tens or hundreds of nodes and an interconnection network. The architecture and implementation of the interconnection network are a key to the performance of the multiprocessor. In order to achieve low latency and high throughput, the interconnection network requires a well designed routing algorithm and an efficient switch design. The interconnection network for a multiprocessor can be in either a regular topology or an irregular topology. With the interconnection network in a regular topology (or regular network), routing is relatively easy to implement. However, for multiprocessor clusters that require scalability, the interconnection network in an irregular topology (or irregular network) is more suitable. Nonetheless, it is relatively difficult to devise an efficient and deadlock-free routing scheme for irregular networks. We have previously proposed a routing scheme called TRAIN (Tree-Based Routing Algorithm for Irregular Networks) for irregular networks used in multiprocessor clusters. In this thesis, we aim at applying TRAIN routing to regular networks in order to achieve cost effectiveness and flexibility. We show that TRAIN can be used in various regular networks, such as 2D mesh, 3D mesh and hypercube, and still possesses the good properties of routing schemes for regular networks. In order to apply TRAIN to various regular networks and still prossess the nice properties of routing schemes for regular networks, we need to come up with techniques to map the routing architecture properly. For example, the X-Y routing in mesh and the E-cube routing in hypercube can be emulated by using TRAIN with a properly designed mapping scheme respectively. These mapping schemes are not trivial. Since TRAIN is based on a tree subnetwork, we can build a spanning tree and then assign a unique ID for each node. The process of building the spanning tree and assigning ID to each node is done during the initialization stage of the system. With the same switches used in irregular network, commonly used routing schemes for regular networks are emulated through tree configuration. Furthermore, when a regular network is faulty, we can easily reconfigure it into a typical irregular network with TRAIN. Hence, excellent flexibility and versatility of the interconnection network are accomplished. In the thesis, we also describe our hardware implementation of the TRAIN switch. With the TRAIN algorithm, the efficiency of distance calculation is the key to the performance of the interconnection network. We demonstrate our implementation with logic circuitry, and use the hardware description language Verilog to show the design details.