| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 87 === In this thesis, we will propose a novel frame based symbol timing recovery architecture and use the ATSC HDTV system as the test vehicle. The proposed methodology has three distinguishing features. First, it separates the loops for the frequency and phase error compensation. The advantages include the large capture range and small steady variation. Second, it incooperates a direct phase compensation mechanism to prevent the phase over run problem commonly seen in the frame based timing recovery systems. Third, it uses the tapped delay line to replace the conventional VCXO. This minimizes the number of external components and the production cost. The system has been simulated thoroughly. The simulation done in MATLAB, Verilog, and HSPICE all indicate that the proposed architecture is feasible and can meet the system requirement. The proposed architecture has been design and implemented as a mixed analog/digital integrated circuit using TSMC SPTM 0.6um technology.
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