| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 87 === The COordinate Rotational DIgital Computer (CORDIC) algorithm is a well-known Digital Signal Processing (DSP) algorithm for computing vector rotation and trigo-nometric functions. The main concept of the CORDIC algorithm is to decompose the de-sired rotation angle into iterations of pre-defined elementary rotation angles. The rotation operation can be performed by simple shift-and-add operations. The simplicity and regu-larity of CORDIC processor makes it very suitable for Very Large Scale Integrated (VLSI) circuit implementation. Nevertheless, the major disadvantage of CORDIC algorithm is its slow computational speed. Hence, it is essential to improve the processing latency.
In the thesis, we consider a cost-efficient architecture, based on that the rotation angle is known in advance, to improve the speed performance of the CORDIC processor. We call it Modified Angle-Recording CORDIC (MAR-CORDIC). In the MAR-CORDIC scheme, we extend the set of rotational sequence from mi = {1, -1} to mi = {1, 0, -1}. Then, we also allow that each the micro-rotation can be performed more than once, so that the MAR-CORDIC can be operated in a more flexible way. On the other hand, we also restrict the maximum iteration number without sacrificing SQNR performance for cost-efficient of hardware implementation. The modifications presented in the thesis improve the speed and reduce the area of CORDIC implementation. The impact of speed performance on the CORDIC processor architecture is also discussed. Finally, we apply the MAR-CORDIC to Fast Fourier Transform (FFT) VLSI architecture. From the example, we can see its effec-tiveness in saving hardware cost in roataion-base circuit.
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